VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

Wen Ta Lee; Bo Han Wu; Jiann Jong Chen; Yuh Shyan Hwang

doi:10.1109/EDSSC.2007.4450129

VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

Wen Ta Lee
, Bo Han Wu
, Jiann Jong Chen
, Yuh Shyan Hwang

電子工程系

研究成果: 書籍/報告/會議論文中的章節 › 會議投稿 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm ².

原文	English
主出版物標題	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
頁面	329-332
頁數	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450129
出版狀態	Published - 2007
事件	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan 持續時間: 20 12月 2007 → 22 12月 2007

出版系列

名字	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
國家/地區	Taiwan
城市	Tainan
期間	20/12/07 → 22/12/07

存取文件

10.1109/EDSSC.2007.4450129

其它文件與鏈接

Link to publication in Scopus

引用此

Lee, W. T., Wu, B. H., Chen, J. J., & Hwang, Y. S. (2007). VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (頁 329-332). 文章 4450129 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450129

@inproceedings{7e1bf841d6a349ad8065cfb0bcd451ec,

title = "VLSI architecture for low power turbo decoder using adaptive sliding window algorithm",

abstract = "In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7\% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92\% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm 2.",

author = "Lee, \{Wen Ta\} and Wu, \{Bo Han\} and Chen, \{Jiann Jong\} and Hwang, \{Yuh Shyan\}",

year = "2007",

doi = "10.1109/EDSSC.2007.4450129",

language = "???core.languages.en\_GB???",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "329--332",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Lee, WT, Wu, BH, Chen, JJ & Hwang, YS 2007, VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. 於 IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450129, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, 頁 329-332, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450129

VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. / Lee, Wen Ta; Wu, Bo Han; Chen, Jiann Jong 等.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 329-332 4450129 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

研究成果: 書籍/報告/會議論文中的章節 › 會議投稿 › 同行評審

TY - GEN

T1 - VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

AU - Lee, Wen Ta

AU - Wu, Bo Han

AU - Chen, Jiann Jong

AU - Hwang, Yuh Shyan

PY - 2007

Y1 - 2007

N2 - In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm 2.

AB - In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm 2.

UR - https://www.scopus.com/pages/publications/43049177930

U2 - 10.1109/EDSSC.2007.4450129

DO - 10.1109/EDSSC.2007.4450129

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:43049177930

SN - 1424406374

SN - 9781424406371

T3 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

SP - 329

EP - 332

BT - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

T2 - IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Y2 - 20 December 2007 through 22 December 2007

ER -

VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此