Simultaneous layer-aware and region-aware partitioning for 3D IC

Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.