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Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition

  • Po Chou Chen
  • , Shu Mei Chang
  • , Hao Chung Kuo
  • , Fu Cheng Chang
  • , Yu An Li
  • , Chao Cheng Ting

研究成果: 期刊貢獻文章同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this research, a 14 nm high-performance computing application-specific integrated circuit was coated with a 5–20 nm Al2O3 thin film by atomic layer deposition in room-temperature conditions to study its performance in terms of reliability with different thicknesses. An open/short test, standby current measurement, interface input/output performance test, and phase-locked loops functional test were used to verify chip performance. Furthermore, an unbiased highly accelerated temperature and humidity stress test and a 72 h wear-out test were used to study the effects of the atomic layer deposition coating. The results showed that the coating thickness of 15 nm provided the best performance in the wear-out test, as well as the unbiased highly accelerated temperature humidity stress. This study demonstrates that room-temperature atomic layer deposition is a promising technique for enhancing the reliability of advanced node semiconductor chips.

原文English
文章編號1308
期刊Coatings
12
發行號9
DOIs
出版狀態Published - 9月 2022

文獻附註

Publisher Copyright:
© 2022 by the authors.

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