摘要
A novel digital-controlled transition current-mode control technique for interleaved power factor corrector (PFC) is proposed in this paper. For the presented technique, the switching period to retain zero-current switching is predicted rather than sampling the current in real time. Moreover, the related turn-ON period is determined by the voltage controller. Therefore, neither zero-current detection nor high-frequency A/D converter for current sampling is required. Moreover, for interleaved topology with masterslave control, a new ON-time compensation technique is proposed to significantly improve the slave inductor-current distortion, and thereby, achieving current sharing control between phases. Experimental results derived from a DSP-based controller are presented for confirmation. The PFC is with 100 Vac/50 Hz input and 400 Vdc output. The power rating is 460 W. Experimental results show that the power factor is higher than 0.98, efficiency is greater than 96%, and the current sharing can be achieved by the proposed ON-time compensation technique. These results confirm the aforementioned claims very well.
| 原文 | English |
|---|---|
| 文章編號 | 5535193 |
| 頁(從 - 到) | 3085-3094 |
| 頁數 | 10 |
| 期刊 | IEEE Transactions on Power Electronics |
| 卷 | 25 |
| 發行號 | 12 |
| DOIs | |
| 出版狀態 | Published - 2010 |
文獻附註
Funding Information:Manuscript received January 10, 2010; revised June 19, 2010; accepted July 20, 2010. Date of current version December 27, 2010. This work was supported by the Hitachi Computer Peripherals Co. Ltd., Japan. Recommended for publication by Associate Editor B. Lehman.
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