FPGA-based digital-controlled power converter designed with universal input meeting 80 plus platinum efficiency code and standby power code for sever power applications

This paper contributes to the design and control of digital-controlled power converter meeting platinum efficiency code and standby power code for sever power applications. Hardware design, control methods and software implementation based upon FPGA will be presented. First, design of hardware and controller is presented, and followed by the loss analysis of power converter to provide a systematic approach to meeting the platinum efficiency code. A feed-forward control for PFC stage with wide range input voltage is presented to provide a constant bandwidth despite of input voltage variation. Two control modes for PSFB converter are presented to meet standby power code. Software implementation based upon FPGA is then included. Experimental results of FPGA-based digital-controlled power converter are presented. It will be shown the standby power is less than 0.5W and light load efficiency is improved to go up to more than 90% for both low line and high line input voltage. Moreover, it will be confirmed that the platinum efficiency code can be met under 20%, 50% and 100% load conditions. These results fully support the claims and contributions of this paper.