摘要
In this paper, a forward converter based on a field programmable gate array (FPGA) technique is presented to obtain ultra fast transient load response. At the same time, a hysteresis voltage-controlled pulse width modulation (PWM) scheme, together with maximum current limiting, is also involved. In addition, methods of approximately estimating the hysteresis band and the output voltage ripple are detailedly illustrated. The design procedure starts from the current slew rate of the output inductor and the output current slew rate from no load to full load. In order to validate this ultra fast transient load response, the experimental results by the proposed topology are compared with those by the conventional topology.
| 原文 | English |
|---|---|
| 頁(從 - 到) | 850-855 |
| 頁數 | 6 |
| 期刊 | IEE Conference Publication |
| 卷 | 2 |
| 出版狀態 | Published - 2004 |
| 事件 | Second International Conference on Power Electronics, Machines and Drives, PEMD 2004 - Edinburgh, United Kingdom 持續時間: 31 3月 2004 → 2 4月 2004 |
指紋
深入研究「Forward converters having ultra fast load transient response with hysteresis band and output voltage ripple considered」主題。共同形成了獨特的指紋。引用此
- APA
- Author
- BIBTEX
- Harvard
- Standard
- RIS
- Vancouver