Enhanced Electrical Performance of Van der Waals Heterostructure

In this study, a novel van der Waals (vdW) heterostructure field-effect transistor (FET) using vdW stacking as next-generation device architecture is demonstrated. The MoS₂/WS₂ heterostructure FET exhibits a large improvement in the drain current and field-effect mobility (from 43.3 to 62.4 cm² V⁻¹ s⁻¹) compared with single MoS₂ FET. Such significant enhancement is mainly due to the charge-transfer effect. The vdW self-encapsulation effect in the device channel also helps to reduce the Schottky barrier height from 120 to 52 meV at the contact interface. Finally, the WS₂/MoS₂/WS₂ double heterostructure FETs further boosts the mobility up to 102.5 cm² V⁻¹ s⁻¹ at room temperature (25 °C) and 169.7 cm² V⁻¹ s⁻¹ at 30 K. The much higher mobility exhibited at the lower temperature indicates the suppression of Coulomb scattering. Thus the electrical performance of the double-heterostructure FETs can be further enhanced.