摘要
This paper proposes a dual-path frequency compensation (DPFC) for implementing on-chip error amplifier (EA). The DPFC uses two operation amplifiers to simultaneously charge and discharge a compensation capacitor. As a result, the equivalent capacitance is significantly multiplied with small additional power and silicon area. Since the slew rate of the EA is increased owing to the small compensation capacitance, the transient response of the buck converter is also enhanced dramatically. A laboratory converter with the DPFC is implemented with 0.35-μm CMOS process. Simulation results demonstrate the converter stability and transient response. The transient recovery time is less than 4 μs for load current changing from 500 mA to 50 mA. With the DPFC, the compensation capacitor is shrunk significantly and no compensation resistor is needed.
| 原文 | English |
|---|---|
| 主出版物標題 | 2015 IEEE 11th International Conference on Power Electronics and Drive Systems, PEDS 2015 |
| 發行者 | Institute of Electrical and Electronics Engineers Inc. |
| 頁面 | 432-436 |
| 頁數 | 5 |
| ISBN(電子) | 9781479944033 |
| DOIs | |
| 出版狀態 | Published - 14 8月 2015 |
| 事件 | 11th IEEE International Conference on Power Electronics and Drive Systems, PEDS 2015 - Sydney, Australia 持續時間: 9 6月 2015 → 12 6月 2015 |
出版系列
| 名字 | Proceedings of the International Conference on Power Electronics and Drive Systems |
|---|---|
| 卷 | 2015-August |
Conference
| Conference | 11th IEEE International Conference on Power Electronics and Drive Systems, PEDS 2015 |
|---|---|
| 國家/地區 | Australia |
| 城市 | Sydney |
| 期間 | 9/06/15 → 12/06/15 |
文獻附註
Publisher Copyright:© 2015 IEEE.
指紋
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