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Applying a counter-based PFM control strategy to an FPGA-based SR forward converter

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5 引文 斯高帕斯(Scopus)

摘要

A field programmable gate arrays (FPGA) technique applied to a forward converter is presented to design a pulse-frequency-modulation (PFM) controller, along with protection peripherals. With only one comparator and without any analogue-to-digital converter (ADC), the information on the feedback output voltage is entirely obtained according to a counter. Besides, the control effort is calculated and used during the present period, thus causing the transient load response to be very fast. In this paper, the operation of this control topology is illustrated, along with some experimental results to demonstrate its effectiveness.

原文English
主出版物標題2006 IEEE Region 10 Conference, TENCON 2006
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)1424405491, 9781424405497
DOIs
出版狀態Published - 2006
事件2006 IEEE Region 10 Conference, TENCON 2006 - Hong Kong, China
持續時間: 14 11月 200617 11月 2006

出版系列

名字IEEE Region 10 Annual International Conference, Proceedings/TENCON
ISSN(列印)2159-3442
ISSN(電子)2159-3450

Conference

Conference2006 IEEE Region 10 Conference, TENCON 2006
國家/地區China
城市Hong Kong
期間14/11/0617/11/06

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