A novel bridge chip between an ATM and ethernet for ADSL in home networks

Guo Ming Sung; Hsiang Yuan Hsieh

doi:10.1109/TCE.2009.5277976

A novel bridge chip between an ATM and ethernet for ADSL in home networks

Guo Ming Sung
, Hsiang Yuan Hsieh

電機工程系

研究成果: 期刊貢獻 › 文章 › 同行評審

3 引文斯高帕斯（Scopus）

摘要

This study presents a novel bridge chip between an Asynchronous Transfer Mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-μm 1P6M CMOS process. The proposed bridge chip is an ASIC designed with Hardware Description Language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.

原文	English
頁（從 - 到）	1200-1207
頁數	8
期刊	IEEE Transactions on Consumer Electronics
卷	55
發行號	3
DOIs	https://doi.org/10.1109/TCE.2009.5277976
出版狀態	Published - 2009

文獻附註

Funding Information:
1This work was supported by National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract No. NSC 95-2221-E-027-138-MY3.

Funding Information:
The authors would like to thank the National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract No. NSC 95-2221-E-027-138-MY3. The Chip Implementation Center (CIC), Taiwan, is appreciated for fabricating the test chip. Ted Knoy is appreciated for his editorial assistance.

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10.1109/TCE.2009.5277976

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引用此

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title = "A novel bridge chip between an ATM and ethernet for ADSL in home networks",

abstract = "This study presents a novel bridge chip between an Asynchronous Transfer Mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-μm 1P6M CMOS process. The proposed bridge chip is an ASIC designed with Hardware Description Language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.",

keywords = "ATM, Asymmetric Digital Subscriber Line (ADSL), Ethernet, Home networks",

author = "Sung, \{Guo Ming\} and Hsieh, \{Hsiang Yuan\}",

note = "Funding Information: 1This work was supported by National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract No. NSC 95-2221-E-027-138-MY3. Funding Information: The authors would like to thank the National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract No. NSC 95-2221-E-027-138-MY3. The Chip Implementation Center (CIC), Taiwan, is appreciated for fabricating the test chip. Ted Knoy is appreciated for his editorial assistance.",

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AB - This study presents a novel bridge chip between an Asynchronous Transfer Mode (ATM) and Ethernet for an asymmetric digital subscriber line (ADSL) in home network which fabricated in a standard 0.18-μm 1P6M CMOS process. The proposed bridge chip is an ASIC designed with Hardware Description Language (HDL) and fabricated using a cell-based digital IC design flow. The proposed chip merges two independent chips; transmitter-end and receiver-end chips, into a single chip, and eliminate the RISC processor to reduce production cost. Moreover, system stability and transmission capacity are enhanced due to the small chip area. Chip specifications are a power supply of 1.8 V and system operating frequency of 50 MHz.

KW - ATM

KW - Asymmetric Digital Subscriber Line (ADSL)

KW - Ethernet

KW - Home networks

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A novel bridge chip between an ATM and ethernet for ADSL in home networks

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