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A Low-Resolution Direct Digital Synthesis Transmitter Architecture Using Dithering for Multiband 5G NR Mobile Applications

  • You Huei Chen
  • , Shu Chen Lin
  • , Jui Hsin Hung
  • , Hao Shun Yang
  • , Jau Horng Chen
  • , Yi Jan Emery Chen

研究成果: 期刊貢獻文章同行評審

5 引文 斯高帕斯(Scopus)

摘要

This letter presents a low-resolution multiband transmitter architecture using direct digital synthesis (DDS) with dithering. Modern modulated signals constructed by a low-resolution digital-to-analog converter (DAC) suffer from quantization errors and distortions. The proposed technique reduces the quantization problems with the use of a proper oversampling ratio (OSR) and the dithering technique. This technique has lower cost and lower complexity compared to conventional transmitters while maintaining linearity performance. A 50-MHz 5G NR 256-quadratic-amplitude modulation (QAM) signal is used for concept validation at bands n1, n40, and n50. The proposed work achieved the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of under-30 dBc and 3.5%, respectively. A single 3-bit 10-GS/s radio frequency (RF) DAC is used where the performance is similar to a conventional transmitter using a pair of 5-bit baseband in-phase and quadrature (IQ) DACs.

原文English
頁(從 - 到)1359-1362
頁數4
期刊IEEE Microwave and Wireless Components Letters
32
發行號11
DOIs
出版狀態Published - 1 11月 2022

文獻附註

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© 2001-2012 IEEE.

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