VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

Wen Ta Lee; Bo Han Wu; Jiann Jong Chen; Yuh Shyan Hwang

doi:10.1109/EDSSC.2007.4450129

VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

Wen Ta Lee
, Bo Han Wu
, Jiann Jong Chen
, Yuh Shyan Hwang

Department of Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm ².

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	329-332
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450129
State	Published - 2007
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan, Taiwan Duration: 20 Dec 2007 → 22 Dec 2007

Publication series

Name	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Country/Territory	Taiwan
City	Tainan
Period	20/12/07 → 22/12/07

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10.1109/EDSSC.2007.4450129

Cite this

Lee, W. T., Wu, B. H., Chen, J. J., & Hwang, Y. S. (2007). VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. In IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 (pp. 329-332). Article 4450129 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007). https://doi.org/10.1109/EDSSC.2007.4450129

@inproceedings{7e1bf841d6a349ad8065cfb0bcd451ec,

title = "VLSI architecture for low power turbo decoder using adaptive sliding window algorithm",

abstract = "In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7\% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92\% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm 2.",

author = "Lee, \{Wen Ta\} and Wu, \{Bo Han\} and Chen, \{Jiann Jong\} and Hwang, \{Yuh Shyan\}",

year = "2007",

doi = "10.1109/EDSSC.2007.4450129",

language = "???core.languages.en\_GB???",

isbn = "1424406374",

series = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

pages = "329--332",

booktitle = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007",

note = "IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 ; Conference date: 20-12-2007 Through 22-12-2007",

}

Lee, WT, Wu, BH, Chen, JJ & Hwang, YS 2007, VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. in IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007., 4450129, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, pp. 329-332, IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007, Tainan, Taiwan, 20/12/07. https://doi.org/10.1109/EDSSC.2007.4450129

VLSI architecture for low power turbo decoder using adaptive sliding window algorithm. / Lee, Wen Ta; Wu, Bo Han; Chen, Jiann Jong et al.
IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007. 2007. p. 329-332 4450129 (IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18um 1P6M process in cell base design flow. When this chip operate at 77MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91×2.17mm 2.

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VLSI architecture for low power turbo decoder using adaptive sliding window algorithm

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