Simultaneous layer-aware and region-aware partitioning for 3D IC

Yung Hao Lai; Yang Lang Chang; Jyh Perng Fang; Jie Lee

doi:10.1109/APCCAS.2016.7804014

Simultaneous layer-aware and region-aware partitioning for 3D IC

Yung Hao Lai
, Yang Lang Chang
, Jyh Perng Fang
, Jie Lee

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.

Original language	English
Title of host publication	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	502-505
Number of pages	4
ISBN (Electronic)	9781509015702
DOIs	https://doi.org/10.1109/APCCAS.2016.7804014
State	Published - 3 Jan 2017
Event	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of Duration: 25 Oct 2016 → 28 Oct 2016

Publication series

Name	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Conference

Conference	2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/16 → 28/10/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Keywords

3D IC
TSV
hMetis
iLap
partitioning
wire-length

Access to Document

10.1109/APCCAS.2016.7804014

Cite this

Lai, Y. H., Chang, Y. L., Fang, J. P., & Lee, J. (2017). Simultaneous layer-aware and region-aware partitioning for 3D IC. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 502-505). Article 7804014 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804014

@inproceedings{c43aff3bd5f84f358af631764ada3b63,

title = "Simultaneous layer-aware and region-aware partitioning for 3D IC",

abstract = "Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.",

keywords = "3D IC, TSV, hMetis, iLap, partitioning, wire-length",

author = "Lai, \{Yung Hao\} and Chang, \{Yang Lang\} and Fang, \{Jyh Perng\} and Jie Lee",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 ; Conference date: 25-10-2016 Through 28-10-2016",

year = "2017",

month = jan,

day = "3",

doi = "10.1109/APCCAS.2016.7804014",

language = "???core.languages.en\_GB???",

series = "2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "502--505",

booktitle = "2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016",

}

Lai, YH, Chang, YL, Fang, JP & Lee, J 2017, Simultaneous layer-aware and region-aware partitioning for 3D IC. in 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016., 7804014, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Institute of Electrical and Electronics Engineers Inc., pp. 502-505, 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, Korea, Republic of, 25/10/16. https://doi.org/10.1109/APCCAS.2016.7804014

Simultaneous layer-aware and region-aware partitioning for 3D IC. / Lai, Yung Hao; Chang, Yang Lang; Fang, Jyh Perng et al.
2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 502-505 7804014 (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Simultaneous layer-aware and region-aware partitioning for 3D IC

AU - Lai, Yung Hao

AU - Chang, Yang Lang

AU - Fang, Jyh Perng

AU - Lee, Jie

PY - 2017/1/3

Y1 - 2017/1/3

N2 - Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.

AB - Through-silicon vias (TSVs) allow the stacking of dies into multilayer structures, and solve connection problems between neighboring tiers for three-dimensional (3D) integrated circuit (IC) technology. Several studies have investigated how to minimize the number of TSVs in 3D ICs, but not much focus on the total wire-length of circuit. However, with the scaling trend of CMOS technology, the power consumption due to routing resources is much higher than the other resources. In this paper, we propose a novel method of simultaneous layer-aware and region-aware partitioning (SLARAP), basing on hMetis, to reduce the number of TSVs and shorten the total wire-length of circuits simultaneously. The gigascale systems research center (GSRC) benchmarks are used as test circuits in our experiments. The experimental results show that our approach works efficiently and it can effectively reduce the total wire-length compared to iLap while considering the TSV number minimization.

KW - 3D IC

KW - TSV

KW - hMetis

KW - iLap

KW - partitioning

KW - wire-length

UR - https://www.scopus.com/pages/publications/85011045332

U2 - 10.1109/APCCAS.2016.7804014

DO - 10.1109/APCCAS.2016.7804014

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85011045332

T3 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

SP - 502

EP - 505

BT - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Y2 - 25 October 2016 through 28 October 2016

ER -

Simultaneous layer-aware and region-aware partitioning for 3D IC

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this