Design and implementation of an L-band PLL frequency synthesizer

This article describes the design and fabrication of an L-band phase-locked loop (PLL) circuit for mobile communication systems. Three functional subcircuits of the PLL - the phase detector (PD), loop filter and VCO - are studied. A Bode diagram to judge the PLL's loop stability and the Matlab program to select an appropriate loop filter with fitted loop stability are also investigated. In addition, a Turbo C program is developed to control the data, clock and enable terminals from the PC print port to manipulate the PLL's channel frequency in mobile communications. Experimental results show that the designed PLL's phase noise improves the VCO's performance by approximately 5 to 6 dBc/Hz. The results demonstrate that the designed frequency synthesizer generates stable, low phase noise and controllable locked signals at the desired channel frequencies in mobile communications.