Combination of fine pitch and high uniformity of lead-free plating-based flip chip solder bumps

Electroplating is by far the most promising process to fabricate fine pitch solder bumps in flip chip. However, rugged surface and poor coplanarity resulted from numerous variable plating parameters generally cause short circuit and broken circuit to affect packaging reliability. With the great demand for decreasing pitch size below 100 um, solder bumps' coplanarity would become more and more important as considering alignment in advanced three-dimensional packaging and WLP (Wafer Level Packaging). This paper aims to provide a creative solder bump fabrication process that is characterized by using a polishing mechanism to transform the plated solder bumps with huge height deviation into smooth and uniform ones. Predominately in mechanical polishing force enables it to polish much wider height deviation, typically affected by poor current distribution in tiny area plating. Equipped with a specific soft non-woven polishing pad and a self-designed substrate holder, the polisher features large MRR (Material Removal Rate), easy manipulation and high efficiency. The final experimental results indicate that the polishing rate in lead-free Sn-Cu solder bumps could reach as fast as 4-5 um/min, almost 50 times faster than CMP (Chemical Mechanical Polishing). The whole coplanarity of solder bumps at 80 um pitch size could be sharply decreased from 33±2.5 um (7.5%) after plating to 28±1 um (3%) after polishing and even 26±0.5 um (1%) after reflow. Most importantly, each single die (6mmx6mm) after reflow could be controlled as accurately as within 0.5%. This proposed polishing mechanism could assist the plating-based solder bumps in precisely getting better coplanarity so as to enhance packaging reliability and yield.