TY - GEN
T1 - Accelerating the transient load response of an FPGA-counter-based SR forward converter
AU - Hwu, K. I.
AU - Yau, Y. T.
PY - 2006
Y1 - 2006
N2 - Accelerating the transient load response is proposed herein and applied to a field programmable gate arrays (FPGA)-counter-based forward converter with synchronous rectification (SR). With only one comparator and without any analog-to-digital converter (ADC), the information on the feedback output voltage is entirely obtained according to a counter. Besides, the transient load response is improved significantly by using the proposed control strategy, especially from heavy load to light load. In this paper, the operation of such a control topology is illustrated, along with some experimental results to verify its effectiveness.
AB - Accelerating the transient load response is proposed herein and applied to a field programmable gate arrays (FPGA)-counter-based forward converter with synchronous rectification (SR). With only one comparator and without any analog-to-digital converter (ADC), the information on the feedback output voltage is entirely obtained according to a counter. Besides, the transient load response is improved significantly by using the proposed control strategy, especially from heavy load to light load. In this paper, the operation of such a control topology is illustrated, along with some experimental results to verify its effectiveness.
UR - https://www.scopus.com/pages/publications/42449140709
U2 - 10.1109/PESC.2006.1711791
DO - 10.1109/PESC.2006.1711791
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AN - SCOPUS:42449140709
SN - 0780397169
SN - 9780780397163
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
BT - 37th IEEE Power Electronics Specialists Conference 2006, PESC'06
T2 - 37th IEEE Power Electronics Specialists Conference 2006, PESC'06
Y2 - 18 June 2006 through 22 June 2006
ER -