A Selective Write Strategy for the Elimination of Write Disturb Errors on Nonvolatile Memory Caches

Recently, the rapid development of modern nonvolatile memories (NVMs) have renovated the designs of computing systems. However, the unique characteristics of NVMs often degrade the performance, reliability, or lifetime of existing designs of the memory-storage subsystem. In particular, the slow write performance and high write energy of many NVMs inspired many research proposals that aim to reduce the NVM write traffic, such as the differential write technique. On the other hand, some NVMs have write disturbance problem, and an NVM cell might be erroneously changed when its neighboring NVM cells are programmed. Although the differential write technique is proven effective in reducing the NVM write traffic, the write disturbance problem might be considerably exacerbated due to the selective random updates to the cells in a machine word, thereby affecting the reliability of data. In this work, we discuss the potential techniques that alleviate write disturbance problem while still providing good perfor-mance/energy of write operations to an NVM-based buffer cache.